Contemporary memory system designs employ a variety of memory devices, including semiconductor memory devices (e.g., dynamic RAM, static RAM, flash memory), magnetic discs and the like. With a wide variety of such devices available, and commonly used, it is a challenge to support all available memory space of, for example, a personal computer, using only a single type of memory device. Particularly, in the field of semiconductor memories, the development of devices to meet the requirements of high density, high-speed read/write operation, access time, low power consumption, etc. is an ongoing challenge, however there is an inevitable limit to technology speed and capacity of semiconductor.
To address this issue, a ferroelectric memory, which is nonvolatile, and therefore can retain data even when power is removed, has been realized through the use of a ferroelectric material, for example lead zirconate titanate (PZT), exhibiting hysterisis characteristics. Several examples of such ferroelectric memory technology are disclosed in the IEEE Journal of Solid-State Circuits, vol. 23, No. 5, pp. 1171.about.1175, October 1988, entitled "An Experimental 512-bit Nonvolatile Memory with Ferroelectric Storage Cell".
As well known in the art, a ferroelectric material has spontaneous polarization characteristics. The direction of the spontaneous polarization is controlled as a function of the direction of an applied electric field. Typical ferroelectric materials include the ABO.sub.3 type of PbZrO.sub.3 molecule. A metal atom, i.e., zirconium (Zr), positioned at the centra of the PbZrO.sub.3 molecule has two stable states in accordance with the directions of an applied electric field. As a result, the ferroelectric material exhibits hysterisis characteristics in electric field and degree of polarization.
Ferroelectric random access memory (hereinafter referred to as "FRAM") is an example of a semiconductor memory device employing the hysterisis characteristics of ferroelectric material. Such FRAMs exhibit nonvolatile data storage characteristics by corresponding the degree of polarization to binary data. They are further capable of performing a read/write operation quickly by using a very last inverse polarization.
A conventional ferroelectric memory cell is now described with reference to FIG. 1 which is a circuit representation of a ferroelectric memory cell MC. The cell MC consists of an access transistor Tr (often referred to as a "select transistor" or "charge transfer transistor"), and a ferroelectric capacitor C.sub.F. Such a configuration is suitable for memory devices with large scale capacity. In each FRAM memory cell MC, the ferroelectric capacitor C.sub.F is comprised of a ferroelectric material inserted between first and second electrodes (referred to as "plate electrodes" or "plates") thereof. The access transistor Tr is connected between a first electrode of capacitor C.sub.F and a bit line BL, and a gate thereof is connected to a word line WL. The second capacitor electrode is coupled to a plate line PL. Since FRAM transistors can be fabricated using a well-known CMOS fabrication technique, the FRAM can be advantageously applied to integration.
FIG. 2 is a hysterisis curve or hysterisis switching loop of the ferroelectric capacitor C.sub.F. In this graph, the abscissa indicates a potential difference V (Volts) between the electrodes of the ferroelectric capacitor C.sub.F, and the ordinate indicates the amount of charge induced to a surface of the ferroelectric material in accordance with spontaneous polarization, i.e., the degree of polarization Q(.mu.C/cm.sup.2).
As shown in FIG. 2, if no electric field is applied to the ferroelectric material with a zero voltage applied thereto, no polarization is evident. When applied voltage is increased in the positive direction of the graph, the degree of polarization is increased from zero up to a point "A", in the positive charge polarization domain. At the point "A", all domains are polarized in one direction and the degree of polarization is maximized. At this level, the degree of polarization, i.e., the amount of charge in the ferroelectric material is indicated as Qs, and the applied voltage as the operation voltage Vcc. Following the initial charge, even though the voltage is lowered again to zero voltage, the degree of polarization is not reduced to zero, but remains at point "B", at a remanent degree of polarization Qr.
When a voltage is applied in the negative direction of the graph, the degree of polarization is changed from point "B" to a point "C" in the negative charge polarization domain. At point "C", all domains of the ferroelectric material are polarized in a reverse direction with respect to the polarization direction at point "A". The degree of polarization is then indicated as - Qs, and the applied voltage as the operation voltage -Vcc. Following the reverse charge, even though the voltage is lowered again to zero voltage, the degree of polarization is not reduced to zero, but remains at a point "D" at a remanent degree of polarization --Qr. If the voltage is increased in the positive direction, the degree of polarization reverses from point "D" to point "A".
As mentioned above, if a voltage is applied temporarily to the ferroelectric capacitor, even though its electrodes may be set to floating state, the polarization direction according to the spontaneous polarization can be continuously maintained. Because of the spontaneous polarization, surface charges of the ferroelectric material are not spontaneously dissipated due to leakage. When the applied voltage is reduced or removed, the polarization direction continues to be maintained.
Read and write operations can be effected in the FRAM by polarization reversal, and therefore the operation speed thereof is determined by the time of such reversal. The speed of polarization reversal in the ferroelectric capacitor is determined by the capacitor area, a thickness of ferroelectric thin film, the applied voltage, etc. The unit of the speed of polarization reversal is commonly measured in microseconds (.mu.s). The FRAM can therefore be operated at a faster rate than electrically erasable and programmable read only memory (EEPROM) or flash memory. Read and write operations of the FRAM will now be described.
In the FRAM, a binary data signal corresponds to remanent points "B" and "D" of the hysterisis loop shown in FIG. 2. Logical "1" corresponds to point "B", and logical "0" corresponds to point "D".
Returning to FIG. 1, at an initial stage of the read and write operation of the FRAM, an operation for sensing data stored in the memory cells is performed. During the sensing operation, the bit line BL is maintained at a floating state. The access transistor Tr is then activated by the word line WL so that the zero voltage on the bit line BL is applied to the first electrode of the ferroelectric capacitor C.sub.F, and a pulse signal of Vcc level is applied to the second electrode thereof via plate line PL. At this time, if a "1" data value is stored in the ferroelectric capacitor C.sub.F, the degree of polarization of the capacitor C.sub.F is varied from the point "B" to the point "D" via the point "C". As a result, a charge amount of dQ is transmitted from the ferroelectric capacitor C.sub.F to the bit line BL, and thereby the voltage on the bit line BL is increased.
Reversely, if a logical data "0" is stored in the capacitor C.sub.F, the degree of polarization of the capacitor C.sub.F is varied from point "D" to point "C" and returns to point "D". In this case, the voltage on the bit line BL does not change. The bit line voltage is compared with a reference voltage by means of a well-known sense circuit. If the bit line voltage is greater than the reference voltage, it is increased to an operational voltage level (i.e., Vcc level). If not, the bit line voltage is lowered again to zero voltage.
Following completion of the above-mentioned data sensing operation, a data read/write operation begins. During a data write operation, a voltage on a data line, for example, a voltage at Vcc level (i.e., logical data "1") or zero level (i.e., logical data "0"), is delivered to the bit line BL by means of a column selector. Following a lapse of a predetermined time amount, a pulse signal is applied to the ferroelectric capacitor C.sub.F. The degree of polarization of the ferroelectric capacitor C.sub.F is then varied from point "B" to point "D" so that a logical data "1" or "0" data is written in the memory cell.
If the sensing operation is performed with respect to a memory cell which stores a logical data "1" (i.e., the degree of polarization of Qr at the point "B") or if a pulse signal is applied to the ferroelectric capacitor C.sub.F which stores a logical data "1", the stored data becomes a logical data "0" (i.e., the degree of polarization of --Qr at the point "D") because of the hysterisis characteristics of the ferroelectric capacitor C.sub.F. Therefore, before the completion of the write operation, it is necessary to allow for the recovery of data states of the respective ferroelectric capacitors C.sub.F of nonvolatile-selected memory cells connected in common to the word line WL to an initial state. This data recovery is called "rewrite" or "restore". The Vcc level of pulse signal is applied once more to the ferroelectric capacitor C.sub.F of the memory cell whose sensing operation is completed. Thus, the degree of polarization of the ferroelectric capacitor CF of each of the nonvolatile-selected memory cells is recovered from --Qr (indicating the logical data "0") at point "D" to Qr (indicating the logical data "1") at point "B".
During a read operation, data on the bit line BL obtained by the data sensing operation is delivered directly to the data bus. During the read operation, if the sensing operation is carried out with respect to the cell which stores a logical data "1", the data stored in the ferroelectric capacitor C.sub.F is changed to a logical data "0". Therefore, before the completion of the read operation, a Vcc pulse is applied once more to the ferroelectric capacitor C.sub.F of the memory cell whose sensing operation is completed. Thus, the degree of polarization of the ferroelectric capacitor C.sub.F recovers from --Qr to Qr at point "B".
A reference cell array for providing the reference voltage to the sense circuit incorporates a plurality of reference cells, each of which comprises an access transistor and a ferroelectric capacitor, as in the memory cell MC. The ferroelectric capacitor of each of the reference cells is similar in size to that of the memory cell MC. That is, it is formed so as to exhibit identical hysterisis characteristics to that of the memory cell MC. As well-known in the art, the reference voltage, which is typically half of the sum of the voltage level of a logical data "1" and the voltage level of a logical data "0", is produced by using two reference cells having the same hysterisis characteristics as that of the memory cell MC, respectively. The generated reference voltage is delivered onto a reference bit line corresponding to a plurality of memory cells.
In applying such a reference cell array to the FRAM, the reference voltage level is half of the sum of the voltage level of a logical data "1" and the voltage level of a logical data "0" (case C), as illustrated in FIG. 3. However, if a ferroelectric capacitor of the reference cell has a degree of polarization which is different from that of each of the corresponding memory cells, then, as a result, the reference voltage therefrom to be provided on the reference bit line may be biased toward either the voltage level of a logical data "1" or the voltage level of a logical data "0". As illustrated in FIG. 3, if the reference voltage level on the reference bit line is biased toward the logic data "1" (case A), the sensing margin for memory cells storing the logical data "1" is decreased. Likewise, if the reference voltage level thereon is biased toward the logical data "0" (case B), the sensing margin for memory cells storing the logical data "0" is decreased.
Unlike dynamic random access memory, it is difficult or impossible to adjust the reference voltage bias level inside a FRAM. Therefore, the possibility of data failure for the memory cells associated with the reference bit line of the biased reference voltage level is more likely increased therein. Accordingly, the reliability of the FRAM is lowered.